1. Field of the Invention
The invention relates generally to the device configuration and manufacturing methods for fabricating the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for reducing the gate to drain coupled charges (Qgd) while providing a drain to source current path for preventing a drain to source resistance.
2. Description of the Related Art
In order to increase the switching speed of a semiconductor power device, it is desirable to reduce the coupling charges between the gates and drain Qgd such that a reduction of a gate to drain capacitance Crss can be reduced. However, conventional device as shown in FIG. 1 has a large amount of coupling charges Qgd between the gates and drain due to the direct coupling between the sidewalls of the trench gates and the drain. Specifically, Kobayashi discloses in a U.S. Pat. No. 6,888,196 entitled “Vertical MOSFET reduced in Cell Size and Method of Producing the Same” a vertical MOSFET device as that shown in FIG. 1.
In order to reduce the capacitance Crss, a double poly gates and double gate oxide layers (a thick gate oxide on trench bottom) formed in trench with lower poly gate connected to source are disclosed in U.S. Pat. Nos. 7,091,573 and 7,183,610. However, formation of the device structures is very complicate and expensive.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the semiconductor power devices such that the above discussed problems and limitations can be resolved.